general description the ds1110l 10-tap delay line is a 3v version of the ds1110. it has 10 equally spaced taps providing delays from 10ns to 500ns. the ds1110l series delay lines provide a nominal accuracy of ?% or ?ns, whichever is greater, at 3.3v and +25?. the ds1110l is character- ized to operate from 2.7v to 3.6v. the ds1110l produces both leading- and trailing-edge delays with equal precision. the device is offered in a standard 14-pin tssop. features ? all-silicon delay line ? 3v version of the ds1110 ? 10 taps equally spaced ? delays are stable and precise ? leading- and trailing-edge accuracy ? delay tolerance ?% or ?ns, whichever is greater, at 3.3v and +25? ? economical ? low-profile 14-pin tssop ? low-power cmos ? ttl/cmos compatible ? vapor phase and ir solderable ? fast-turn prototypes ? delays specified over commercial and industrial temperature ranges ? custom delays available ds1110l 3v 10-tap silicon delay line _____________________________________________ maxim integrated products 1 14 13 12 11 10 9 8 1 2 3 4 5 6 7 v cc tap1 tap3 tap5 tap4 tap2 n.c. in top view tap7 tap9 tap10 gnd tap8 tap6 tssop (173mil) ds1110l pin configuration ordering information xx-xxxx; rev 1; 11/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part tem p range pin- package total delay ( ns) * ds1110le-100 -40? to +85? 14 tssop (173mil) 100 ds1110le-125 -40? to +85? 14 tssop (173mil) 125 ds1110le-150 -40? to +85? 14 tssop (173mil) 150 ds1110le-175 -40? to +85? 14 tssop (173mil) 175 ds1110le-200 -40? to +85? 14 tssop (173mil) 200 ds1110le-250 -40? to +85? 14 tssop (173mil) 250 ds1110le-300 -40? to +85? 14 tssop (173mil) 300 DS1110LE-350 -40? to +85? 14 tssop (173mil) 350 ds1110le-400 -40? to +85? 14 tssop (173mil) 400 ds1110le-450 -40? to +85? 14 tssop (173mil) 450 ds1110le-500 -40? to +85? 14 tssop (173mil) 500 *custom delays are available. applications communications equipment medical devices automated test equipment pc peripheral devices
ds1110l 3v 10-tap silicon delay line 2 ______________________________________________________________________ absolute maximum ratings dc electrical characteristics (-40? to +85?, v cc = 2.7v to 3.6v.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on any pin relative to ground .................-0.5v to +6.0v operating temperature range ...........................-40 c to +85 c storage temperature range .............................-55 c to +125 c soldering temperature...................see ipc/jedec j-std-020a parameter symbol conditions min typ max units supply voltage v cc (note 1) 2.7 3.3 3.6 v high-level input voltage v ih (note 1) 2.2 v cc + 0.3 v low-level input voltage v il (note 1) -0.3 +0.8 v input leakage current i i 0v v i v cc -1.0 +1.0 a active current i cc v cc = max, period = min (note 2) 40 150 ma high-level output current i oh v cc = min, v oh = 2.3v -1.0 ma low-level output current i ol v cc = min, v ol = 0.5v 12 ma ac electrical characteristics (-40? to +85?, v cc = 2.7v to 3.6v.) parameter symbol conditions min typ max units input pulse width t wi (note 6) 10% of tap 10 ns +25?, 3.3v (notes 3, 5, 6, 7, 9) -2 table 1 +2 0? to +70? (notes 4?) -3 table 1 +3 input to tap delay (delays 40ns) t plh t phl -40? to +85? (notes 4?) -4 table 1 +4 ns +25?, 3.3v (notes 3, 5, 6, 7, 9) -5 table 1 +5 0? to +70? (notes 4?) -8 table 1 +8 input to tap delay (delays > 40ns) t plh t phl -40? to +85? (notes 4?) -13 table 1 +13 % power-up time t pu 100 ms input period period (note 8) 2 (t wi )ns
ds1110l 3v 10-tap silicon delay line _____________________________________________________________________ 3 note 1: all voltages are referenced to ground. note 2: measured with outputs open. note 3: initial tolerances are with respect to the nominal value at +25? and v cc = 3.3v for both leading and trailing edges. note 4: temperature and voltage tolerances are with respect to the nominal delay value over stated temperature range and a 2.7v to 3.6v range. note 5: intermediate delay values are available on a custom basis. note 6: see test conditions section. note 7: all tap delays tend to vary unidirectionally with temperature or voltage changes. for example, if tap 1 slows down, all other taps also slow down; tap 3 can never be faster than tap 2. note 8: pulse width and period specifications may be exceeded; however, accuracy is application sensitive (decoupling, layout, etc.). note 9: for tap 1 delays greater than 20ns, the tolerance is ?ns or ?%, whichever is greater. capacitance (t a = +25?.) typical operating characteristics (v cc = 3.3v, t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units input capacitance c in 510pf -2 -1 0 1 2 3 4 -3 change in delay (%) vs. temperature ds1110l-250 ds1110l toc04 temperature ( c) change in delay (%) 60 35 10 -15 -40 85 rising edge falling edge change in delay (%) vs. temperature ds1110l-500 ds1110l toc03 temperature ( c) change in delay (%) 60 35 10 -15 -4 -3 -2 -1 0 1 2 3 4 5 6 -5 -40 85 rising edge falling edge -0.3 -0.2 -0.1 0 0.1 0.2 0.3 -0.4 delay change (%) vs. v cc ds1110l-250 ds1110l toc02 v cc (v) change in delay (%) 3.3 3.0 2.7 3.6 raising edge falling edge delay change (%) vs. v cc ds1110l-500 ds1110l toc01 v cc (v) change in delay (%) 3.3 3.0 -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 -0.35 2.7 3.6 raising edge falling edge
ds1110l 3v 10-tap silicon delay line 4 ______________________________________________________________________ typical operating characteristics (continued) (v cc = 3.3v, t a = +25?, unless otherwise noted.) 1.0 5 10 15 20 25 0 0.1 10 active current vs. input frequency ds1110l-500 ds1110l toc08 frequency (mhz) current (ma) v cc = 3.6v 15pf load on each tap active current vs. input frequency ds1110l-250 ds1110l toc07 frequency (mhz) current (ma) 10 1 5 10 15 20 25 30 35 40 45 50 0 0.1 100 v cc = 3.6v 15pf load on each tap ds1110l toc06 0.5 0.4 0.3 0.2 0.1 2.00e-03 4.00e-03 6.00e-03 8.00e-03 1.00e-02 1.20e-02 1.40e-02 1.60e-02 1.80e-02 0.00e+00 00.6 output current low vs. output voltage low output voltage low (v) output current low (a) v cc = 2.7v output current high vs. output voltage high ds1110l toc05 output voltage high (v) output current high (a) 2.6 2.5 2.3 2.4 2.2 2.1 -1.60e-02 -1.40e-02 -1.20e-02 -1.00e-02 -8.00e-03 -6.00e-03 -4.00e-03 -2.00e-03 0.00e+0 -1.80e-02 2.0 2.7 v cc = 2.7v pin name function 1 in input 2 n.c. no connection 7 gnd ground 13, 3, 12, 4, 11, 5, 10, 6, 9, 8 tap 1?ap 10 tap output number 14 v cc 2.7v to 3.6v pin description
detailed description the ds1110l 10-tap delay line is a 3v version of the ds1110. it has 10 equally spaced taps providing delays from 10ns to 500ns. the device is offered in a standard 14-pin tssop. the ds1110l series delay lines provide a nominal accuracy of ?% or ?ns, whichever is greater, at 3.3v and +25?. the ds1110l is character- ized to operate from 2.7v to 3.6v. the ds1110l repro- duces the input-logic state at the tap 10 output after a fixed delay as specified by the dash-number suffix of the part number ( table 1 ). the ds1110l produces both lead- ing- and trailing-edge delays with equal precision. each tap is capable of driving up to 10 74ls-type loads. dallas semiconductor can customize standard products to meet specific needs. figure 1 is the ds1110_l logic diagram and figure 2 shows the timing diagram for the silicon delay line. ds1110l 3v 10-tap silicon delay line _____________________________________________________________________ 5 10% 10% in tap1 tap2 tap9 tap10 10% 10% figure 1. logic diagram part t o t a l d el a y ( n s ) delay/tap (ns) ds1110le-100 100 10 ds1110le-125 125 12.5 ds1110le-150 150 15 ds1110le-175 175 17.5 ds1110le-200 200 20 ds1110le-250 250 25 ds1110le-300 300 30 DS1110LE-350 350 35 ds1110le-400 400 40 ds1110le-450 450 45 ds1110le-500 500 50 table 1. part number by delay (t phl , t plh ) v il in out 0.6v v ih t rise 2.4v 1.5v 1.5v 1.5v 1.5v 1.5v 0.6v 2.4v period t wi t plh t plh t fall t wi figure 2. timing diagram: silicon delay line
ds1110l terminology period: the time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t wi (pulse width): the elapsed time on the pulse between the 1.5v point on the leading edge and the 1.5v point on the trailing edge, or the 1.5v point on the trailing edge and the 1.5v point on the leading edge. t rise (input rise time): the elapsed time between the 20% and the 80% point on the leading edge of the input pulse. t fall (input fall time): the elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. t plh (time delay rising): the elapsed time between the 1.5v point on the leading edge of the input pulse and the 1.5v point on the leading edge of any tap out- put pulse. t phl (time delay, falling): the elapsed time between the 1.5v point on the trailing edge of the input pulse and the 1.5v point on the trailing edge of any tap out- put pulse. test setup description figure 3 illustrates the hardware configuration used for measuring the timing parameters on the ds1110l. a precision pulse generator under software control pro- duces the input waveform. time delays are measured by a time interval counter (20ps resolution) connected 3v 10-tap silicon delay line 6 ______________________________________________________________________ pulse generator time interval counter vhf switch control unit stop device under test z0 = 50 ? start figure 3. test circuit
ds1110l 3v 10-tap silicon delay line maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 _____________________ 7 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. between the input and each tap. each tap is selected and connected to the counter by a vhf switch-control unit. all measurements are fully automated, with each instrument controlled by a central computer over an ieee-488 bus. output each output is loaded with the equivalent of one 450 ? resistor in parallel with a 15pf capacitor. delay is mea- sured at the 1.5v level on the rising and falling edge. input condition ambient temperature +25? ?? supply voltage (v cc ) 3.3v ?.1v high = 3.0v ?.1v input pulse low = 0.0v ?.1v source impedance 50 ? max rise and fall time 2ns max pulse width 500ns (1? for - 500ns) period 1? (2? for - 500ns) table 2. test conditions package information for the latest package outline information, go to www.maxim-ic. com/packages . note: above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. chip information transistor count: 6813
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs ds1110le-200 part number table notes: see the ds1110le-200 quickview data sheet for further information on this product family or download the ds1110le-200 full data sheet (pdf, 112kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis ds1110le-200+ tssop;14 pin;173 dwg: 56-g2015-000b (pdf) use pkgcode/variation: u14+1 * -40c to +85c rohs/lead-free: yes materials analysis ds1110le-200 tssop;14 pin;173 dwg: 56-g2015-000b (pdf) use pkgcode/variation: u14-1 * -40c to +85c rohs/lead-free: no materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y
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